(1) FIELD OF THE INVENTION
This invention relates to a test site and method of using a test site to monitor the extent of mask misalignment and buried contact trench formation in MOS FET integrated circuits.
(2) DESCRIPTION OF THE RELATED ART
The process of forming buried contacts frequently results in the formation of buried contact trenches. These trenches are a problem particularly for shallow junction devices. This invention describes a method and test site for monitoring the extent of these trenches.
U.S. Pat. No. 5,637,186 to Liu et al. describes a method and monitor test site to measure semiconductor device dimensions.
U.S. Pat. No. 5,633,173 to Bae describes a method of forming dummy dies at edge portions of a wafer. The wafers are analyzed in a defect detecting apparatus and the defect data is used to inspect for process defects at subsequent process steps.
U.S. Pat. No. 5,296,917 to Kusonose et al. describes a method of inspecting and measuring the accuracy with which patterns are written on an integrated circuit wafer.
U.S. Pat. No. 5,721,146 to Liaw et al. describes a method of forming a buried contact within a trench etched into the silicon substrate.
U.S. Pat. No. 5,654,231 to Liang et al. describes a method of eliminating a buried contact trench in the formation of buried contacts.
U.S. Pat. No. 5,668,051 to Chen et al. describes a method of forming buried contacts having reduced series resistance. The buried contact trench is filled with doped polysilicon which reduces the series resistance between the buried contact and the source/drain regions.
U.S. Pat. No. 5,004,658 to Hjulstrom describes a system and method for adjusting the capacitance of thin film capacitors. Adjustment patterns comprising parallel adjustment lines are used. The adjustment lines are offset aligned with corresponding lines of a photolithographic mask during the formation of the metal capacitor plates.